1. Field of the Disclosure
The disclosure relates to a semiconductor device and, to a method for fabricating the device.
2. Brief Description of Related Technology
Due to high integration of semiconductor devices, a contact area between a bit line and an active region of a semiconductor substrate is reduced. This reduction makes it is difficult to contact the bit line with the contact area. In the manufacturing process of semiconductor devices, a landing plug contact is formed for stable electric connection between top and bottom patterns. The active region of the semiconductor substrate is electrically connected to the bit line through the landing plug contact. When the bit line is formed, an interlayer insulating film is etched, and a bit line contact process is performed to expose the landing plug contact.
A resistance is increased through a bit line contact and a landing plug contact, and a flowing current amount is decreased to generate a Time to Write and Read (tWR) fail. In the tWR fail, a resistance is increased with resistance increase of the landing plug contact while data stored in a capacitor of a memory cell are transmitted into a bit line so that the data stored in the cell are not recognized in the bit line.
FIGS. 1a to 1e are cross-sectional diagrams illustrating a conventional method for forming a bit line contact of a semiconductor device. Referring to FIG. 1a a gate structure 125 are formed over a semiconductor substrate 100 including a device isolation structure 105. The gate structure 125 having a deposition structure including a gate insulating film (not shown), a gate conductive pattern 110, a gate metal pattern 115 and a gate hard mask pattern 120. The gate conductive pattern 110 includes a polysilicon layer, and the gate metal pattern 115 includes a tungsten silicide layer. The gate hard mask pattern 120 includes a nitride film. A spacer 130 is formed at a sidewall of the gate structure 125. The spacer 130 includes one selected from the group consisting of an oxide film, a nitride film, and combinations thereof.
Referring to FIG. 1b, an interlayer insulating film (not shown) is formed over the semiconductor substrate 100 and the gate structure 125 including the spacer 130, and a landing plug contact region is etched to form a landing plug contact hole (not shown). A polysilicon layer (not shown) is formed to fill the landing plug contact hole, and planarized to expose the gate hard mask pattern 120, thereby obtaining a landing plug contact 140.
Referring to FIG. 1c, an insulating film 145 for bit line contact is formed over the gate hard mask pattern 120, the landing plug contact 140 and the interlayer insulating film 135. The insulating film 145 includes one selected from the group consisting of high temperature oxide (HTO), tetraethoxysilane (TEOS), undoped silicate glass (USG), borophosphosilica glass (BPSG), and combinations thereof. A photoresist pattern 150 that defines a bit line contact region is formed over the insulating film 145.
Referring to FIG. 1d, the insulating film 145 is etched with the photoresist pattern 150 as an etching mask to form a bit line contact hole 155 that exposes the landing plug contact 140. The etching process for forming the bit line contact hole 155 is performed by a dry etching method. The photoresist pattern 150 is removed.
Referring to FIG. 1e, a barrier film 160 is formed over the landing plug contact 140 and the insulating film 145 including the bit line contact hole 155. A bit line 170 is formed to fill the bit line contact hole 155 with a bit line conductive layer 165. The barrier film 160 includes one selected from the group consisting of a titanium film, a titanium nitride film, and combinations thereof.
In the conventional method, a bit line contact and a landing plug contact are formed to increase a resistance between two interfaces. An additional process for forming a landing plug contact complicates a process step. A signal of the bit line passes through the bit line contact and the landing plug contact to increase a resistance. As a result, a current amount decreases to generate a tWR fail. As a design rule of the device is decreased, an overlap margin between the active region and the bit line is decreased so that a contact area is reduced.